Power Conversion and Distribution Unit

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The Power Conversion and Distribution Unit (PCDU) is an EPS module that splits the main quasi-regulated bus into multiple regulated buses at the voltages and currents needed for the specific subsystems.


The PCDU employs a centralised architecture.

DC-DC switching step-down voltage regulators are used to split and convert the quasi-regulated main bus voltage to deliver the appropriate voltage levels to each subsystem as specified in the power budget. To increase reliability in case any one regulator fails, back-up regulators in parallel OR'd configuration with the primary are required. However, a regulator that fails short-circuit in parallel with its own backup would cause a critical failure. To remedy this, diode behaviour is needed. Either an actual diode or an N-MOSFET can implement this, with the N-MOSFET having lower on-resistance and therefore the least heat dissipation and forward drop. To use the N-MOSFET on the high side, an ideal controller IC is needed to charge-pump the gate to the required levels.

In this simple OR'd configuration, the load sharing is uncontrolled and effectively random, so any given regulator must be able to carry the full load of its bus. The regulators are critical components keeping the satellite alive, but have backups, so each independent regulator is considered a Level 2 component and a 70% derating is used to calculate the maximum derated current.

The tightest constraint currently defined on voltage accuracy is +/- 100mV as required by the OEM-7 GPS. The voltage ripple must be controlled to within this window. One approach is to provide a higher accuracy, lower-efficiency 3.3V bus that uses a non-switching linear regulator to drop directly from the main bus voltage as close as possible to the GPS. RF payloads usually require low ripple as well to avoid amplifier noise, so a similar approach may be needed there.

The main bus voltage is also available, allowing limited distributed-style versatility. A fully distributed design would abdicate responsibility for regulation to the point-of-load, and simply provide a separately switched main bus connection for each subsystem.


LTC4358 is an ideal diode controller. The LTC4358 has a built-in MOSFET with a 5A maximum load, which provides well over a 25% margin of safety above the maximum bus load calculated in the power budget. At the time of this writing LTC4358 is available in an easy-to-place 16-TSSOP package. However, the voltage required to supply the IC itself is a minimum of 9V.


LM5050MKX is an ideal diode controller from TI that's designed to control an external MOSFET. This increases component count and board space but allows us to tailor the MOSFET power rating to our needs. The chip can switch voltages of 1.0-75V which is ideal for the low-voltage buses, but must be supplied with a 5.0-75V voltage for its own use. LM5050 should be disabled when not in use to eliminate its quiescent power draw.


Power is bussed from the regulator stages to the individual subsystems via the PC/104 Bus. The load rating of PC/104 connectors such as 952-2219-ND] and 3M10622-ND is 3A. Boeing's derating guideline has an applicable section on connectors. A power rail is considered a Level 1 component as it has no backup, and a failure would end the mission. The recommend derating is therefore 50%, yielding a derated max current of 1.5A if the rail is a single conductor. The qualification load the 3V3 bus must support exceeds this, at 3.3917A. The solution is to use a rail of three conductors in parallel, yielding a derated max of 4.5A. The conductors could be tied together on each board all the way up the PC/104 bus or kept separate. In the latter case, the connected loads must be carefully divided between the three conductors to avoid overloading any single one. One such possible division is tabulated below:

3V3 Rail A:

System Peak Power (W) Peak Load (A) Citation
RF Sensors & LEDs 0.234825 0.0712 RF Budget
OBC 0.390 0.118 Kabir on Slack
Magnetorquers 0.6006 0.182 ADCS PDR
Reaction Wheels 2.0691 0.627 ADCS PDR

3V3 Rail B:

System Peak Power (W) Peak Load (A) Citation
Camera FPGA 3.3 1.0 TE0725 Datasheet
Camera Sensor (Visible) 0.891 0.270 OV5642 Datasheet
Camera Sensor (IR) 0.891 0.270 OV5642 Datasheet

3V3 Rail C:

System Peak Power (W) Peak Load (A) Citation
GPS 1.7985 0.545 OEM-7 Data Sheet

Load switches on each bus must be implemented as well, with control signals interfaced to the Computing subsystem.


Ideally, the verification testing should occur in a controlled thermal vacuum chamber.

  • Attach thermistors across the PCDU system to monitor temperature of the ICs and bus traces, log data using an MCU (or more expensively, use a thermal camera)
  • Attach a rheostat as a configurable load to each bus. Use a multimeter to log the voltage across each rheostat
  • Apply the qualification load as defined in the power budget to each bus until thermal equilibrium is achieved (design is rejected if this breaks the board)
  • Save the voltage data and report the effects of increased load on regulator accuracy (design is rejected if the voltage accuracy falls out of spec at any time)
  • Save the temperature data and report the hottest locations in the design


  • As this is an interface where loads will be applied and removed, transient voltages and in-rush currents are likely. In-rush limiters and TVS diodes at the off-board interface points would be prudent. It is expected that each connected subsystem will have its own current-limiting PTC fuse at its input. However, if possible, each bus will have a PTC fuse limiting it to its total rated load as well.